1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a semiconductor integrated circuit including a plurality of semiconductor chips.
2. Description of the Related Art
In general, packaging technology for a semiconductor integrated circuit has been continuously developed for reduction in size and increase in mounting reliability. Various techniques for a stack package are being developed in line with a demand for smaller size and higher performance of electrical and electronic products.
A term ‘stack’ commonly referred in the semiconductor industry means that two or more semiconductor chips or packages are piled up. In accordance with such a stack package, for example, a semiconductor memory device may have a memory capacity twice or more compared to a memory capacity that may be implemented in a semiconductor integration process. Furthermore, researches and development for a stack package are being accelerated because the memory capacity, mounting density, and efficiency in the use of a mounting area may be increased by the stack package.
A stack package may be fabricated using a method of stacking selective semiconductor chips and packaging the stacked semiconductor chips at once or a method of stacking packaged selective semiconductor chips. The selective semiconductor chips of a stack package are electrically coupled through metal wires or chip through vias.